﻿/**
  ******************************************************************************
  * @file    Libraries/Device/JS32T031/JS32T031_LL_Driver/inc/js32t031_ll_ust.h
  * @author  JUSHENG Application Team
  * @version V1.0.0
  * @date    02-19-2022
  * @brief   This file contains all the UST LL firmware functions.
  ******************************************************************************
  * @attention
  *
  * <h2><center>&copy; COPYRIGHT 2022 JUSHENG</center></h2>
  *
  *
  *
  ******************************************************************************
  */ 
  
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __JS32T031_LL_UST_H
#define __JS32T031_LL_UST_H

#ifdef __cplusplus
 extern "C" {
#endif

/* Includes ------------------------------------------------------------------*/
#include "js32t031.h"
     
/** @addtogroup JS32T031_StdPeriph_Driver JS32T031 Driver
  * @{
  */
     
/** @addtogroup ust_interface_gr UST Driver
  * @ingroup  JS32T031_StdPeriph_Driver
  * @{
  */ 

/** @addtogroup UST_LL_Driver UST LL Driver
  * @ingroup  ust_interface_gr
  * @brief Mainly the driver part of the UST module, which includes \b UST \b Register 
  * \b Constants, \b UST \b Exported \b Constants, \b UST \b Exported \b Struct, \b UST
  * \b Data \b transfers \b functions, \b UST \b Initialization \b and \b UST \b Configuration 
  * \b And \b Interrupt \b Handle \b function.
  * @{
  */

/* Exported types ------------------------------------------------------------*/

/* Exported constants --------------------------------------------------------*/

/** @defgroup UST_LL_Register_Constants UST LL Register Constants
  * @ingroup  UST_LL_Driver
  * @brief    UST LL register constant table definition
  *
  *
@verbatim   
  ===============================================================================
                                Register Constants
  ===============================================================================  
  
    Register Constants mainly encapsulates each bit in each group in the UST 
    register. In the process of configuration, the macro definition can be directly 
    called to configure the UST register, mainly for convenience. Understand the 
    configuration of the UST.
    
@endverbatim
  *
  * @{
  */

/***** UST_MODE Register *****/
/*! RW, UST mode selection  
 * 00 : Reserved  
 * 01 : UART mode  
 * 10 : SPI mode  
 * 11 : TIMER mode  
 */
#define LL_UST_MODE_SEL(n)                                  (((n)&0x3) << 0)


/***** UST_CON0 Register *****/
/*! RW, URAT MODE, UART done interrupt enable  
 * 0 : disable  
 * 1 : enable, interrupt occurs when UART_DONE_PEND is 1  
 */
#define LL_UST_CON0_UART_DONE_IE                            (1UL << 16)

/*! RW, URAT MODE, URAT send or receive enable  
 * 0 : RX EN  
 * 1 : TX EN  
 */
#define LL_UST_CON0_UART_TX_EN                              (1UL << 5)

/*! RW, URAT MODE, URAT_WIRE_MODE Single or double enable  
 * 0 : RX EN  
 * 1 : TX EN  
 */
#define LL_UST_CON0_UART_WIRE_MODE_EN                       (1UL << 2)

/*! RW, SPI MODE, SPI done interrupt enable  
 * 0 : disable  
 * 1 : enable, interrupt occurs when SPI_DONE_PEND is 1  
 */
#define LL_UST_CON0_SPI_DONE_IE                             (1UL << 16)

/*! RW, SPI MODE, SPI transfert from the low bit enable  
 * 0: the high bit first  
 * 1: the low bit first  
 */
#define LL_UST_CON0_SPI_LSBF_EN                             (1UL << 6)

/*! RW, SPI MODE, SPI send or receive enable  
 * 0 : RX EN  
 * 1 : TX EN
 */  
#define LL_UST_CON0_SPI_TX_EN                               (1UL << 5)

/*! RW, SPI MODE, SPI CS pin control output  
 * 0: output low  
 * 1: output high  
 */
#define LL_UST_CON0_SPI_CS_SET                              (1UL << 4)

/*! RW, SPI MODE, SPI need sync input data enable  
 * 0: disable  
 * 1: enable  
 */
#define LL_UST_CON0_SPI_SYNC_EN                             (1UL << 3)

/*! RW, SPI MODE, SPI three wire mode enable  
 * 0: disable  
 * 1: enable  
 */
#define LL_UST_CON0_SPI_WIRE_MODE_EN                        (1UL << 2)

/*! RW, SPI MODE, SPI CPOL, CPHA set  
 * CPOL CPHA  
 * 00: mode 0 :clk idle 0, first rising edge sampling, second falling edge output data  
 * 01: mode 1 :clk idle 0, second falling edge sampling, first rising edge output data  
 * 10: mode 2 :clk idle 1, first falling edge sampling, second rising edge output data  
 * 11: mode 3 :clk idle 1, second rising edge sampling, first falling edge output data  
 */
#define LL_UST_CON0_SPI_CPOL_CPHA_SET(n)                    ((n & 0x03) << 0)

/*! RW, TIMER MODE, TIMER done interrupt enable  
 * 0 : disable  
 * 1 : enable, interrupt occurs when TIMER_DONE_PEND is 1  
 */
#define LL_UST_CON0_TIMER_DONE_IE                           (1UL << 16)


/*! RW, TIMER MODE, TIMER prescaler set  
 */
#define LL_UST_CON0_TIMER_PWM_DAED_ZONE_SET(n)              ((n & 0x1F) << 9)

/*! RW, TIMER MODE, TIMER PWM_LED_MODE  
 * 0 : not stop  
 * 1 : stop  
 */
#define LL_UST_CON0_TIMER_PWM_LED_MODE                      (1UL << 8)

/*! RW, TIMER MODE, TIMER PWM_UD_HOLD  
 * 0 : not stop  
 * 1 : stop  
 */
#define LL_UST_CON0_TIMER_PWM_UD_HOLD                       (1UL << 7)

/*! RW, TIMER MODE, TIMER PWM3_POL  
 * 0 : not negation  
 * 1 : negation  
 */
#define LL_UST_CON0_TIMER_PWM3_POL                          (1UL << 6)

/*! RW, TIMER MODE, TIMER PWM2_POL  
 * 0 : not negation  
 * 1 : negation  
 */
#define LL_UST_CON0_TIMER_PWM2_POL                          (1UL << 5)

/*! RW, TIMER MODE, TIMER PWM1_POL  
 * 0 : not negation  
 * 1 : negation  
 */
#define LL_UST_CON0_TIMER_PWM1_POL                          (1UL << 4)

/*! RW, TIMER MODE, TIMER PWM0_POL  
 * 0 : not negation  
 * 1 : negation  
 */
#define LL_UST_CON0_TIMER_PWM0_POL                          (1UL << 3)

/*! RW, TIMER MODE, TIMER PWM0-3 POL set  
 */
#define LL_UST_CON0_TIMER_PWM_POL_SET(n)                    ((n & 0xF) << 3)


/*! RW, TIMER MODE, TIMER prescaler set  
 */
#define LL_UST_CON0_TIMER_PSC_SET(n)                        (((n)&0x7) << 0)


/***** UST_BAUD Register *****/
/*! RW, URAT MODE, UART baud rate set  
 * URAT baud rate = APB_CLK/(UART_BAUD+1)  
 * Note: UART_BAUD >=6 should be configured, otherwise the input signal will be filtered by the internal filter.  
 */
#define LL_UST_BAUD_UART_BAUD(n)                            (((n)&0xFFFF) << 0)

/*! RW, SPI MODE, SPI baud rate set  
 * SPI baud rate = APB_CLK/(2*(SPI_BAUD+1))  
 */
#define LL_UST_BAUD_SPI_BAUD(n)                             (((n)&0xFFFF) << 0)

/*! RW, TIMER MODE, TIMER count cycle set  
 */
#define LL_UST_BAUD_TIMER_PRD(n)                            (((n)&0xFFFF) << 0)


/***** UST_PRD_BUF Register *****/
/*! RW, UST_PRD_BUF count registers  
 */
#define LL_UST_TIMER_PRD_BUF(n)                             (((u32)(n)&0xFFFF) << 0)

/***** UST_CMP01 Register *****/
/*! RW, TIMER_CMP0 count registers  
 */
#define LL_UST_TIMER_CMP0(n)                                (((u32)(n)&0xFFFF) << 0)

/*! RW, TIMER_CMP1 count registers  
 */
#define LL_UST_TIMER_CMP1(n)                                (((u32)(n)&0xFFFF) << 16)


/***** UST_CMP01_BUF Register *****/
/*! RW, TIMER_CMP0_BUF count registers  
 */
#define LL_UST_TIMER_CMP0_BUF(n)                            (((u32)(n)&0xFFFF) << 0)

/*! RW, TIMER_CMP1_BUF count registers  
 */
#define LL_UST_TIMER_CMP1_BUF(n)                            (((u32)(n)&0xFFFF) << 16)

/*! RW, PWM_BIT_STREAM count registers  
 */
#define LL_UST_PWM_BIT_STREAM(n)                            (((u32)(n)&0xFFFFFFFF) << 0)


/***** UST_CMP23 Register *****/
/*! RW, TIMER_CMP2 count registers  
 */
#define LL_UST_TIMER_CMP2(n)                                (((u32)(n)&0xFFFF) << 0)

/*! RW, TIMER_CMP3 count registers  
 */
#define LL_UST_TIMER_CMP3(n)                                (((u32)(n)&0xFFFF) << 16)

/*! RW, PWM_BIT_STREAM_BUF count registers  
 */
#define LL_UST_PWM_BIT_STREAM_BUF(n)                        (((u32)(n)&0xFFFFFFFF) << 0)


/***** UST_CMP23_BUF Register *****/
/*! RW, TIMER_CMP2_BUF count registers  
 */
#define LL_UST_TIMER_CMP2_BUF(n)                            (((u32)(n)&0xFFFF) << 0)

/*! RW, TIMER_CMP3_BUF count registers  
 */
#define LL_UST_TIMER_CMP3_BUF(n)                            (((u32)(n)&0xFFFF) << 16)

/*! RW, PWM_LED_FRAME_CNT count registers  
 */
#define LL_UST_PWM_LED_FRAME_CNT(n)                         (((u32)(n)&0x7) << 24)

/*! RW, PWM_LED_BIT_CNT count registers  
 */
#define LL_UST_PWM_LED_BIT_CNT(n)                           (((u32)(n)&0x1F) << 16)

/*! RW, PWM_LED_FRAME_SET count registers  
 */
#define LL_UST_PWM_LED_FRAME_SET(n)                         ((n & 0x7) << 8)

/*! RW, PWM_LED_BIT_SET count registers  
 */
#define LL_UST_PWM_LED_BIT_SET(n)                           ((n & 0x1F) << 0)


/***** UST_CNT Register *****/
/*! RW, TIMER count registers  
 * read: TIMER current count value  
 * wirte: When idle, write any value to start counting from 0
 * wirte: When working, write any value to stop counting and count to 0
 */
#define LL_UST_CNT_TIMER_CNT(n)                             (((n)&0xFFFF) << 0)


/***** UST_STA Register *****/
/*! RW, UST MODE, UART/SPI/TIMER done pending  
 * Software write 1 clear 0, write 0 invalid  
 */
#define LL_UST_STA_DONE_PENDING                             (1UL << 16)

/*! RC, UST MODE, UART buffer overflow pending  
 */
#define LL_UST_STA_UART_BUFF_OVF_PENDING                    (1UL << 3)

/*! RC, UST UART frame error pendig  
 * 0 : err empty  
 * 1 : err not empty  
 */
#define LL_UST_STA_UART_FERR_PENDING                        (1UL << 2)

/*! RO, UST buffer pending  
 * 0 : buffer empty  
 * 1 : buffer not empty  
 */
#define LL_UST_STA_BUFFER_PENDING                           (1UL << 1)

/*! RO, UST start pending  
 * 0 : UST idle  
 * 1 : UST working  
 */
#define LL_UST_STA_START_PENDING                            (1UL << 0)


/*! Ust Uart baud
 */
#define LL_UST_UART_BAUDRATE_300                               (300)
#define LL_UST_UART_BAUDRATE_600                               (600)
#define LL_UST_UART_BAUDRATE_1200                              (1200)
#define LL_UST_UART_BAUDRATE_2400                              (2400)
#define LL_UST_UART_BAUDRATE_4800                              (4800)
#define LL_UST_UART_BAUDRATE_9600                              (9600)
#define LL_UST_UART_BAUDRATE_19200                             (19200)
#define LL_UST_UART_BAUDRATE_38400                             (38400)
#define LL_UST_UART_BAUDRATE_56000                             (56000)
#define LL_UST_UART_BAUDRATE_57600                             (57600)
#define LL_UST_UART_BAUDRATE_115200                            (115200)
#define LL_UST_UART_BAUDRATE_230400                            (230400)
#define LL_UST_UART_BAUDRATE_256000                            (256000)
#define LL_UST_UART_BAUDRATE_460800                            (460800)
#define LL_UST_UART_BAUDRATE_512000                            (512000)
#define LL_UST_UART_BAUDRATE_600000                            (600000)
#define LL_UST_UART_BAUDRATE_750000                            (750000)
#define LL_UST_UART_BAUDRATE_921600                            (921600)

/**
  * @}
  */

/** @defgroup UST_LL_Exported_Constants UST LL Exported Constants
  * @ingroup  UST_LL_Driver
  * @brief    UST LL external constant definition
  *
@verbatim   
  ===============================================================================
                                Exported Constants
  ===============================================================================  
  
    Exported Constants mainly restricts the partial configuration of the abstraction 
    layer by using the form of enumeration to facilitate the use and understanding of 
    the module configuration. For the specific enumeration meaning, please refer to 
    the annotation of each module.

@endverbatim
  *
  * @{
  */
  
/***** DRIVER API *****/



/***** LL API *****/

/**
  * @brief Enumeration constant for UART mode en
  */
typedef enum {
    /*! Reserved
     */
    LL_UST_RESERVED__MODE               = 0x00,
    /*! Uart enable
     */
    LL_UST_UART_MODE                    = 0x01,
    /*! SPI enable
     */
    LL_UST_SPI_MODE                     = 0x02,
    /*! Timer enable
     */
    LL_UST_TIMER_MODE                   = 0x03,
} TYPE_ENUM_LL_UST_MODE;

/**
  * @brief Enumeration constant of UST_BAUD
  */
typedef enum {
    /*! Uart disable
     */
    LL_UST_IE_DISABLE                   = 0,
    /*! Uart enable
     */
    LL_UST_IE_ENABLE                    = 1,
} TYPE_ENUM_LL_UST_BAUD_SET;


/**
  * @brief UST0 SPI mode enum type, consistent with the spec definition.
  * @note LL_UST_SPI_MODE_0 represents the first valid rising edge to start data acquisition.  
  *       LL_UST_SPI_MODE_1 represents the second valid falling edge to start data acquisition.  
  *       LL_UST_SPI_MODE_2 represents the first valid falling edge to start data acquisition.  
  *       LL_UST_SPI_MODE_3 represents the second valid rising edge to start data acquisition.  
  */
typedef enum {
    /*! spi mode 0
     */
    LL_UST_SPI_MODE_0                   = 0,
    /*! spi mode 1
     */
    LL_UST_SPI_MODE_1                   = 1,
    /*! spi mode 2
     */   
    LL_UST_SPI_MODE_2                   = 2,
    /*! spi mode 3
     */
    LL_UST_SPI_MODE_3                   = 3,
} TYPE_ENUM_LL_UST_SPI_MODE;

typedef enum {
    /*! spi normal mode
     */
    LL_UST_SPI_NORMAL_MODE               = 0,
    /*! ust spi three mode
     */
    LL_UST_SPI_THREE_WIRE_MODE           = 1,
} TYPE_ENUM_LL_UST_SPI_WIRE_MODE;

/**
  * @brief TIMER mode enum type, meter time fractional frequency.
  */
typedef enum {
    /*! fractional frequency 1
     */
    LL_UST_TIMER_PSC_NONE               = 0x00,
    /*! fractional frequency 2
     */
    LL_UST_TIMER_PSC_2                  = 0x01,
    /*! fractional frequency 4
     */
    LL_UST_TIMER_PSC_4                  = 0x02,
    /*! fractional frequency 8
     */
    LL_UST_TIMER_PSC_8                  = 0x03,
    /*! fractional frequency 16
     */
    LL_UST_TIMER_PSC_16                 = 0x04,
    /*! fractional frequency 32
     */
    LL_UST_TIMER_PSC_32                 = 0x05,
    /*! fractional frequency 64
     */
    LL_UST_TIMER_PSC_64                 = 0x06,
    /*! fractional frequency 128
     */
    LL_UST_TIMER_PSC_128                = 0x07,
} TYPE_ENUM_LL_UST_TIMER_PSC;


/**
  * @brief TIMER mode enum type, pwm led mode frame.
  */
typedef enum {
    /*! PWM LED MODE 1 FRAME
     */
    LL_UST_TIMER_PWM_LED_1_FRAME         = 0x0,
    /*! PWM LED MODE 2 FRAME
     */
    LL_UST_TIMER_PWM_LED_2_FRAME,
    /*! PWM LED MODE 3 FRAME
     */
    LL_UST_TIMER_PWM_LED_3_FRAME,
    /*! PWM LED MODE 4 FRAME
     */
    LL_UST_TIMER_PWM_LED_4_FRAME,
    /*! PWM LED MODE 5 FRAME
     */
    LL_UST_TIMER_PWM_LED_5_FRAME,
    /*! PWM LED MODE 6 FRAME
     */
    LL_UST_TIMER_PWM_LED_6_FRAME,
    /*! PWM LED MODE 7 FRAME
     */
    LL_UST_TIMER_PWM_LED_7_FRAME,
    /*! PWM LED MODE 8 FRAME
     */
    LL_UST_TIMER_PWM_LED_8_FRAME,
} TYPE_ENUM_LL_UST_TIMER_PWM_LED_FRAME;

/**
  * @brief TIMER mode enum type, pwm led mode bit.
  */
typedef enum {
    /*! PWM LED MODE 1 BIT
     */
    LL_UST_TIMER_PWM_LED_1_BIT         = 0x0,
    /*! PWM LED MODE 2 BIT
     */
    LL_UST_TIMER_PWM_LED_2_BIT,
    /*! PWM LED MODE 3 BIT
     */
    LL_UST_TIMER_PWM_LED_3_BIT,
    /*! PWM LED MODE 4 BIT
     */
    LL_UST_TIMER_PWM_LED_4_BIT,
    /*! PWM LED MODE 5 BIT
     */
    LL_UST_TIMER_PWM_LED_5_BIT,
    /*! PWM LED MODE 6 BIT
     */
    LL_UST_TIMER_PWM_LED_6_BIT,
    /*! PWM LED MODE 7 BIT
     */
    LL_UST_TIMER_PWM_LED_7_BIT,
    /*! PWM LED MODE 8 BIT
     */
    LL_UST_TIMER_PWM_LED_8_BIT,
    /*! PWM LED MODE 9 BIT
     */
    LL_UST_TIMER_PWM_LED_9_BIT,
    /*! PWM LED MODE 10 BIT
     */
    LL_UST_TIMER_PWM_LED_10_BIT,
    /*! PWM LED MODE 11 BIT
     */
    LL_UST_TIMER_PWM_LED_11_BIT,
    /*! PWM LED MODE 12 BIT
     */
    LL_UST_TIMER_PWM_LED_12_BIT,
    /*! PWM LED MODE 13 BIT
     */
    LL_UST_TIMER_PWM_LED_13_BIT,
    /*! PWM LED MODE 14 BIT
     */
    LL_UST_TIMER_PWM_LED_14_BIT,
    /*! PWM LED MODE 15 BIT
     */
    LL_UST_TIMER_PWM_LED_15_BIT,
    /*! PWM LED MODE 16 BIT
     */
    LL_UST_TIMER_PWM_LED_16_BIT,
    /*! PWM LED MODE 17 BIT
     */
    LL_UST_TIMER_PWM_LED_17_BIT,
    /*! PWM LED MODE 18 BIT
     */
    LL_UST_TIMER_PWM_LED_18_BIT,
    /*! PWM LED MODE 19 BIT
     */
    LL_UST_TIMER_PWM_LED_19_BIT,
    /*! PWM LED MODE 20 BIT
     */
    LL_UST_TIMER_PWM_LED_20_BIT,
    /*! PWM LED MODE 21 BIT
     */
    LL_UST_TIMER_PWM_LED_21_BIT,
    /*! PWM LED MODE 22 BIT
     */
    LL_UST_TIMER_PWM_LED_22_BIT,
    /*! PWM LED MODE 23 BIT
     */
    LL_UST_TIMER_PWM_LED_23_BIT,
    /*! PWM LED MODE 24 BIT
     */
    LL_UST_TIMER_PWM_LED_24_BIT,
    /*! PWM LED MODE 25 BIT
     */
    LL_UST_TIMER_PWM_LED_25_BIT,
    /*! PWM LED MODE 26 BIT
     */
    LL_UST_TIMER_PWM_LED_26_BIT,
    /*! PWM LED MODE 27 BIT
     */
    LL_UST_TIMER_PWM_LED_27_BIT,
    /*! PWM LED MODE 28 BIT
     */
    LL_UST_TIMER_PWM_LED_28_BIT,
    /*! PWM LED MODE 29 BIT
     */
    LL_UST_TIMER_PWM_LED_29_BIT,
    /*! PWM LED MODE 30 BIT
     */
    LL_UST_TIMER_PWM_LED_30_BIT,
    /*! PWM LED MODE 31 BIT
     */
    LL_UST_TIMER_PWM_LED_31_BIT,
    /*! PWM LED MODE 32 BIT
     */
    LL_UST_TIMER_PWM_LED_32_BIT,
} TYPE_ENUM_LL_UST_TIMER_PWM_LED_BIT;


/***** LL API AND DRIVER API *****/


/**
  * @}
  */

/** @defgroup UST_LL_Exported_Struct UST LL Exported Struct
  * @ingroup  UST_LL_Driver
  * @brief    UST LL external configuration structure definition
  *
@verbatim   
  ===============================================================================
                                Exported Struct
  ===============================================================================  

    Exported Struct mainly extracts the UST registers from the API, and abstracts 
    the structure. As long as it implements the low coupling between the registers 
    and the registers, the user only needs to configure the structure of the abstraction 
    layer and call hal_ust_init. Function, you can configure the UST module without 
    involving the configuration of the collective register.

@endverbatim
  *
  * @{
  */

/**
  * @breif UST UART init struct
  */
typedef struct __ll_ust_uart_init {
    /*! UART baud
    */
    u32                                     baudrate;
    /*! UART interrupt en,
    */
    FunctionalState                         uart_interrupt_en;
    /*! UART WIRE MODE,
    */
    FunctionalState                         wire_mode_choose;
} TYPE_LL_UST_UART_INIT;

/**
  * @breif UST SPI init struct
  */
typedef struct __ll_ust_spi_init {
    /*! Configure the CPOL CPHA mode of the SPI module.
    */
    TYPE_ENUM_LL_UST_SPI_MODE               spi_cpol_cpha;
    /*! SPI 3 - line mode control
    */
    TYPE_ENUM_LL_UST_SPI_WIRE_MODE          spi_wire_mode;
    /*! SPI baud 1k unit
    */
    u32                                     spi_frequency;
    /*! SPI IE enable,
    */
    FunctionalState                         spi_done_ie_en;
    /*! SPI data low order first send/receive enable
    */
    FunctionalState                         spi_lsbf_en;
    /*! SPI TX and RX,
    */
    FunctionalState                         spi_tx_rx_choose;
    /*! SPI CS signal control
    */
    FunctionalState                         spi_cs;
    /*! The SPI receives synchronization of input signals
    */
    FunctionalState                         spi_sync_en;
} TYPE_LL_UST_SPI_INIT;

/**
  * @breif UST TIMER init struct
  */
typedef struct __ll_ust_timer_init {
    /*! Configure the data sampling mode of the SPI module.
    */
    TYPE_ENUM_LL_UST_TIMER_PSC              timer_psc;
    /*! TIMER PRD counting cycle control.
    */
    u16                                     timer_period;
    /*! TIMER IE enable.
    */
    FunctionalState                         timer_done_ie_en;
} TYPE_LL_UST_TIMER_INIT;

//**********************************************************************//
/**
  * @breif UST TIMER cfg struct
  */
typedef struct __ll_ust_timer_pwm_cfg {
    /*! PWM DEAD ZONE.
    */
    u16                                     pwm_dead_zone;
    /*! PWM0 duty.
    */
    u16                                     pwm0_duty;
    /*! PWM1 duty.
    */
    u16                                     pwm1_duty;
    /*! PWM2 duty.
    */
    u16                                     pwm2_duty;
    /*! PWM3 duty.
    */
    u16                                     pwm3_duty;
    /*! TIMER PWM0 - PWM3 POL.
    */
    u8                                      timer_pwm_pol       : 4;
} TYPE_LL_UST_TIMER_PWM_CFG;
/***********************************************************************/

/**
  * @breif UST TIMER cfg struct
  */
typedef struct __ll_ust_timer_pwm_led_cfg {
    /*! BIT 0 duty.
    */
    u16                                     bit_0_duty;
    /*! BIT 0 duty..
    */
    u16                                     bit_1_duty;
    /*! TIMER PWM LED MODE FRAME.
    */
    TYPE_ENUM_LL_UST_TIMER_PWM_LED_FRAME    led_mode_frame;
    /*! TIMER PWM LED MODE BIT.
    */
    TYPE_ENUM_LL_UST_TIMER_PWM_LED_BIT      led_mode_bit;
    /*! TIMER PWM0 POL.
    */
    FunctionalState                         pwm_led_pol;
} TYPE_LL_UST_TIMER_PWM_LED_MODE_CFG;


/**
  * @breif UST ie cfg
  */
typedef struct __ll_ust_ie_cfg {
    /*! Time out time configure.unit is bit rate time.
    */
    u16                                 timeout_len;
} TYPE_LL_UST_IE_CFG;



/** @defgroup UST_LL_Inti_Cfg UST LL Initialization And Configuration
  * @brief    UST LL Initialization And Configuration
  *
@verbatim   
  ===============================================================================
                        Initialization And Configuration
  ===============================================================================  

    This subsection provides a set of functions allowing to manage the UST data 
    Initialization and Configuration.
    
    how to use?

@endverbatim
  *
  * @{
  */

/**
  * @brief  uart_init
  * @param  p_ust : pointer to the hardware UST_TypeDef
  * @param  p_init: pointer to the init stuct TYPE_LL_UST_INIT
  * @retval None
  */
void ll_ust_uart_init(UST_TypeDef *p_uart, TYPE_LL_UST_UART_INIT *p_init);

/**
  * @brief  spi_init
  * @param  p_ust : pointer to the hardware UST_TypeDef
  * @param  p_init: pointer to the init stuct TYPE_LL_UST_INIT
  * @retval None
  */
void ll_ust_spi_init(UST_TypeDef *p_spi, TYPE_LL_UST_SPI_INIT *p_init);

/**
  * @brief  timer_init
  * @param  p_ust : pointer to the hardware UST_TypeDef
  * @param  p_init: pointer to the init stuct TYPE_LL_UST_INIT
  * @retval None
  */
void ll_ust_timer_init(UST_TypeDef *p_timer, TYPE_LL_UST_TIMER_INIT *p_init);

/**
  * @brief  ust_timer_pwm_cfg
  * @param  p_timer : pointer to the hardware UST_TypeDef
  * @param  pwm_cfg: pointer to the init stuct TYPE_LL_UST_TIMER_PWM_CFG
  * @retval None
  */
void ll_ust_timer_pwm_cfg(UST_TypeDef *p_timer, TYPE_LL_UST_TIMER_PWM_CFG *pwm_cfg);
 
/**
  * @brief  ust_timer_pwm_led_mode_cfg
  * @param  p_timer : pointer to the hardware UST_TypeDef
  * @param  pwm_led_cfg: pointer to the init stuct TYPE_LL_UST_TIMER_PWM_LED_MODE_CFG
  * @retval None
  */
void ll_ust_timer_pwm_led_mode_cfg(UST_TypeDef *p_timer, TYPE_LL_UST_TIMER_PWM_LED_MODE_CFG *pwm_led_cfg);

/**
  * @brief  ust_uart_interrupt_enable
  * @param  p_ust : pointer to the hardware UST_TypeDef
  * @retval None
  */
void ll_ust_uart_interrupt_enable(UST_TypeDef *p_ust);

/**
  * @brief  ust_uart_interrupt_disable
  * @param  p_ust : pointer to the hardware UST_TypeDef
  * @retval None
  */
void ll_ust_uart_interrupt_disable(UST_TypeDef *p_ust);

/**
  * @brief  Link layer UST UART interrupt get
  * @param  p_uart: The structure pointer of the UART is selected
  * @retval result
  */
#define LL_UST_UART_DONE_INTERRUPT_GET(p_ust)                   ((p_ust)->UST_CON0 & LL_UST_CON0_UART_DONE_IE)

/**
  * @brief  ust_uart_choose_tx
  * @param  p_ust : pointer to the hardware UST_TypeDef
  * @retval None
  */
void ll_ust_uart_tx_enable(UST_TypeDef *p_ust);

/**
  * @brief  ust_uart_choose_rx
  * @param  p_ust : pointer to the hardware UST_TypeDef
  * @retval None
  */
void ll_ust_uart_rx_enable(UST_TypeDef *p_ust);

/**
  * @brief  Gets the current state of the UST UART about tx_rx
  * @param  p_ust: The structure pointer of the UST is selected
  * @retval result
  */
#define LL_UST_UART_TX_RX_EN_GET(p_ust)                    ((p_ust)->UST_CON0 & LL_UST_CON0_UART_TX_EN)

/**
  * @brief  Single/double line mode
  * @param  p_ust : pointer to the hardware UST_TypeDef
  * @param  tx_data: data
  * @retval None
  */
void ll_ust_uart_wire_mode_choose_single(UST_TypeDef *p_ust);

/**
  * @brief  Single/double line mode
  * @param  p_ust : pointer to the hardware UST_TypeDef
  * @param  tx_data: data
  * @retval None
  */
void ll_ust_uart_wire_mode_choose_double(UST_TypeDef *p_ust);

/**
  * @brief  Gets the current state of the UST about UART_WIRE_MODE
  * @param  p_ust: The structure pointer of the UST is selected
  * @retval result
  */
#define LL_UST_UART_WIRE_MODE_GET(p_ust)                        ((p_ust)->UST_CON0 & LL_UST_CON0_URAT_WIRE_MODE_EN)

/**
  * @brief  ust uart irq tx
  * @param  p_uart: The structure pointer of the UST group (UART) is selected.
  * @param  tx_data: tx uart data.
  * @retval result.
  * @note   uart tx done pending need clear in irq interrupt,and tx next data in the uart irq interrupt.
  */
void ll_ust_uart_irq_tx(UST_TypeDef *p_ust, u8 tx_data);

/**
  * @brief  ust_uart_tx_data
  * @param  p_ust : pointer to the hardware UST_TypeDef
  * @param  tx_data: data
  * @retval None
  */
void ll_ust_uart_tx_data(UST_TypeDef *p_ust, u8 tx_data);

/**
  * @brief  ust_uart_rx_data
  * @param  p_ust : pointer to the hardware UST_TypeDef
  * @param  rx_data: data
  * @retval None
  */
void ll_ust_uart_rx_data(UST_TypeDef *p_ust, u8 *rx_data);

/**
  * @brief  uart baudrate set
  * @param  p_uart: The structure pointer of the UST group is selected.
  * @param  baudrate: uart baudrate.
  * @retval result.
  */
void ll_ust_uart_baudrate_set(UST_TypeDef *p_uart, u32 baudrate);

/**
  * @brief  ust_spi_interrupt_enable
  * @param  p_ust : pointer to the hardware UST_TypeDef
  * @retval None
  */
void ll_ust_spi_interrupt_enable(UST_TypeDef *p_ust);

/**
  * @brief  ust_spi_interrupt_disable
  * @param  p_ust : pointer to the hardware UST_TypeDef
  * @retval None
  */
void ll_ust_spi_interrupt_disable(UST_TypeDef *p_ust);

/**
  * @brief  Link layer UST SPI interrupt get
  * @param  p_uart: The structure pointer of the UART is selected
  * @retval result
  */
#define LL_UST_SPI_DONE_INTERRUPT_GET(p_ust)                ((p_ust)->UST_CON0 & LL_UST_CON0_SPI_DONE_IE)

/**
  * @brief  ust_spi_lsbf_choose
  * @param  p_ust : pointer to the hardware UST_TypeDef
  * @retval None
  */
void ll_ust_spi_lsbf_H_enable(UST_TypeDef *p_ust);

/**
  * @brief  ust_spi_lsbf_choose
  * @param  p_ust : pointer to the hardware UST_TypeDef
  * @retval None
  */
void ll_ust_spi_lsbf_L_enable(UST_TypeDef *p_ust);

/**
  * @brief  Gets the current state of the SPI about LSBF
  * @param  p_ust: The structure pointer of the UST is selected
  * @retval result
  */
#define LL_UST_SPI_LSBF_GET(p_ust)                          ((p_ust)->UST_CON0 & LL_UST_CON0_SPI_LSBF_EN)

/**
  * @brief  ll_ust_spi_cpol_cpha_set
  * @param  p_ust : pointer to the hardware UST_TypeDef
  * @retval None
  */
void ll_ust_spi_cpol_cpha_set(UST_TypeDef *p_ust, TYPE_ENUM_LL_UST_SPI_MODE spi_cpol_cpha_mode);

/**
  * @brief  ust_spi_choose_tx
  * @param  p_ust : pointer to the hardware UST_TypeDef
  * @retval None
  */
void ll_ust_spi_tx_enable(UST_TypeDef *p_ust);

/**
  * @brief  ust_spi_choose_rx
  * @param  p_ust : pointer to the hardware UST_TypeDef
  * @retval None
  */
void ll_ust_spi_rx_enable(UST_TypeDef *p_ust);

/**
  * @brief  Gets the current state of the UST SPI about tx_rx
  * @param  p_ust: The structure pointer of the UST is selected
  * @retval result
  */
#define LL_UST_SPI_TX_RX_PATTERN_GET(p_ust)                 ((p_ust)->UST_CON0 & LL_UST_CON0_SPI_TX_EN)

/**
  * @brief  ust_spi_cs_set
  * @param  p_ust : pointer to the hardware UST_TypeDef
  * @retval None
  */
void ll_ust_spi_cs_high(UST_TypeDef *p_ust);

/**
  * @brief  ust_spi_cs_clr
  * @param  p_ust : pointer to the hardware UST_TypeDef
  * @retval None
  */
void ll_ust_spi_cs_low(UST_TypeDef *p_ust);

/**
  * @brief  Gets the current state of the SPI about CS
  * @param  p_ust: The structure pointer of the UST is selected
  * @retval result
  */
#define LL_UST_SPI_CS_GET(p_ust)                            ((p_ust)->UST_CON0 & LL_UST_CON0_SPI_CS_SET)

/**
  * @brief  ust_spi_sync_enable
  * @param  p_ust : pointer to the hardware UST_TypeDef
  * @retval None
  */
void ll_ust_spi_sync_enable(UST_TypeDef *p_ust);

/**
  * @brief  ust_spi_sync_disable
  * @param  p_ust : pointer to the hardware UST_TypeDef
  * @retval None
  */
void ll_ust_spi_sync_disable(UST_TypeDef *p_ust);

/**
  * @brief  UST SPI slave sync enable get
  * @param  p_uart: The structure pointer of the UART is selected
  * @retval result
  */
#define LL_UST_CON0_SPI_SYNC_EN_GET(p_ust)                  ((p_ust)->UST_CON0 & LL_UST_CON0_SPI_SYNC_EN)

/**
  * @brief  ust_spi_wire_mode_set
  * @param  p_ust : pointer to the hardware UST_TypeDef
  * @retval None
  */
void ll_ust_spi_wire_mode_set(UST_TypeDef *p_ust, TYPE_ENUM_LL_UST_SPI_WIRE_MODE wire_mode);

/**
  * @brief  UST SPI slave sync enable get
  * @param  p_uart: The structure pointer of the UART is selected
  * @retval result
  */
#define LL_UST_CON0_SPI_WIRE_MODE_EN_GET(p_ust)             ((p_ust)->UST_CON0 & LL_UST_CON0_SPI_WIRE_MODE_EN)

/**
  * @brief  ust_spi_cpol_cpha_set
  * @param  p_ust : pointer to the hardware UST_TypeDef
  * @retval None
  */
void ust_spi_cpol_cpha_set(UST_TypeDef *p_ust, TYPE_ENUM_LL_UST_SPI_MODE mode);

/**
  * @brief  UST SPI slave sync enable get
  * @param  p_uart: The structure pointer of the UART is selected
  * @retval result
  */
#define LL_UST_CON0_SPI_CPOL_CPHA_GET(p_ust)                ((p_ust)->UST_CON0 & 0x03)

/**
  * @brief  ust_spi_tx_data
  * @param  p_ust : pointer to the hardware UST_TypeDef
  * @param  tx_data: data
  * @retval None
  */
void ll_ust_spi_tx_byte(UST_TypeDef *p_ust, u8 tx_data);

/**
  * @brief  ust_spi_rx_data
  * @param  p_ust : pointer to the hardware UST_TypeDef
  * @param  rx_data: data
  * @retval None
  */
void ll_ust_spi_rx_byte(UST_TypeDef *p_ust, u8 *rx_data);

/**
  * @brief  spi baudrate set
  * @param  p_uart: The structure pointer of the UST group is selected.
  * @param  baudrate: uart baudrate.
  * @retval result.
  */
void ll_ust_spi_baudrate_set(UST_TypeDef *p_ust, u32 baudrate);

/**
  * @brief  Link layer stop SPI or IIC
  * @param  p_spi: SPI or IIC group address
  * @retval none
  */
void ll_ust_spi_stop(UST_TypeDef *p_ust);

/**
  * @brief  ust_timer_interrupt_enable
  * @param  p_ust : pointer to the hardware UST_TypeDef
  * @retval None
  */
void ll_ust_timer_interrupt_enable(UST_TypeDef *p_ust);

/**
  * @brief  ust_timer_interrupt_disable
  * @param  p_ust : pointer to the hardware UST_TypeDef
  * @retval None
  */
void ll_ust_timer_interrupt_disable(UST_TypeDef *p_ust);

/**
  * @brief  Link layer UST TIMER interrupt get
  * @param  p_uart: The structure pointer of the UART is selected
  * @retval result
  */
#define LL_UST_TIMER_DONE_INTERRUPT_GET(p_ust)              ((p_ust)->UST_CON0 & LL_UST_CON0_TIMER_DONE_IE)

/**
  * @brief  ll_ust_timer_psc_set
  * @param  p_ust : pointer to the hardware UST_TypeDef
  * @param  data : The data of TYPE_ENUM_LL_UST_TIMER_PSC
  * @retval None
  */
void ll_ust_timer_psc_set(UST_TypeDef *p_ust, TYPE_ENUM_LL_UST_TIMER_PSC data);

/**
  * @brief  Link layer UST TIMER PSC get
  * @param  p_uart: The structure pointer of the UST is selected
  * @retval result
  */
#define LL_UST_TIMER_PSC_GET(p_ust)                         (LL_UST_CON0_TIMER_PSC_SET((p_ust)->UST_CON0))

/**
  * @brief  ust_timer_pwm_dead_zone_write
  * @param  p_ust : pointer to the hardware UST_TypeDef
  * @retval None
  */
void ll_ust_timer_pwm_dead_zone_write(UST_TypeDef *p_ust, u16 data);

/**
  * @brief  Link layer UST TIMER PWM DEAD ZONE state get
  * @param  p_uart: The structure pointer of the UST0 is selected
  * @retval result
  */
#define LL_UST_CON0_TIMER_PWM_DEAD_ZONE_GET(p_ust)          ((p_ust->UST_CON0 >> 9) & 0x1f)

/**
  * @brief  ust_timer_pwm_led_mode_disable
  * @param  p_ust : pointer to the hardware UST_TypeDef
  * @retval None
  */
void ll_ust_timer_pwm_led_mode_disable(UST_TypeDef *p_ust);

/**
  * @brief  ust_timer_pwm_led_mode_enable
  * @param  p_ust : pointer to the hardware UST_TypeDef
  * @retval None
  */
void ll_ust_timer_pwm_led_mode_enable(UST_TypeDef *p_ust);

/**
  * @brief  Link layer UST TIMER PWM LED MODE state get
  * @param  p_uart: The structure pointer of the UST0 is selected
  * @retval result
  */
#define LL_UST_TIMER_DONE_PWM_LED_MODE_GET(p_ust)           ((p_ust)->UST_CON0 & LL_UST_CON0_TIMER_PWM_LED_MODE)

/**
  * @brief  ust timer pwm updata hold enable
  * @param  p_ust : pointer to the hardware UST_TypeDef
  * @retval None
  */
void ll_ust_timer_pwm_updata_hold_enable(UST_TypeDef *p_ust);

/**
  * @brief  ust timer pwm updata hold disable
  * @param  p_ust : pointer to the hardware UST_TypeDef
  * @retval None
  */
void ll_ust_timer_pwm_updata_hold_disable(UST_TypeDef *p_ust);

/**
  * @brief  Link layer UST TIMER PWM UD HOLD get
  * @param  p_uart: The structure pointer of the UST0 is selected
  * @retval result
  */
#define LL_UST_TIMER_DONE_PWM_UD_HOLD_GET(p_ust)            ((p_ust)->UST_CON0 & LL_UST_CON0_TIMER_PWM_UD_HOLD)

/**
  * @brief  ust_timer_pwm3_pol_enable
  * @param  p_ust : pointer to the hardware UST_TypeDef
  * @retval None
  */
void ll_ust_timer_pwm3_pol_enable(UST_TypeDef *p_ust);

/**
  * @brief  ust_timer_pwm3_pol_disable
  * @param  p_ust : pointer to the hardware UST_TypeDef
  * @retval None
  */
void ll_ust_timer_pwm3_pol_disable(UST_TypeDef *p_ust);

/**
  * @brief  Link layer UST TIMER PWM3 POL get
  * @param  p_uart: The structure pointer of the UST0 is selected
  * @retval result
  */
#define LL_UST_TIMER_PWM3_POL_GET(p_ust)                    ((p_ust)->UST_CON0 & LL_UST_CON0_TIMER_PWM3_POL)

/**
  * @brief  ust_timer_pwm2_pol_enable
  * @param  p_ust : pointer to the hardware UST_TypeDef
  * @retval None
  */
void ll_ust_timer_pwm2_pol_enable(UST_TypeDef *p_ust);

/**
  * @brief  ust_timer_pwm3_pol_disable
  * @param  p_ust : pointer to the hardware UST_TypeDef
  * @retval None
  */
void ll_ust_timer_pwm2_pol_disable(UST_TypeDef *p_ust);

/**
  * @brief  Link layer UST TIMER PWM2 POL get
  * @param  p_uart: The structure pointer of the UST0 is selected
  * @retval result
  */
#define LL_UST_TIMER_PWM2_POL_GET(p_ust)                    ((p_ust)->UST_CON0 & LL_UST_CON0_TIMER_PWM2_POL)

/**
  * @brief  ust_timer_pwm1_pol_enable
  * @param  p_ust : pointer to the hardware UST_TypeDef
  * @retval None
  */
void ll_ust_timer_pwm1_pol_enable(UST_TypeDef *p_ust);

/**
  * @brief  ust_timer_pwm1_pol_disable
  * @param  p_ust : pointer to the hardware UST_TypeDef
  * @retval None
  */
void ll_ust_timer_pwm1_pol_disable(UST_TypeDef *p_ust);

/**
  * @brief  Link layer UST TIMER PWM1 POL get
  * @param  p_uart: The structure pointer of the UST0 is selected
  * @retval result
  */
#define LL_UST_TIMER_PWM1_POL_GET(p_ust)                    ((p_ust)->UST_CON0 & LL_UST_CON0_TIMER_PWM1_POL)

/**
  * @brief  ust_timer_pwm0_pol_enable
  * @param  p_ust : pointer to the hardware UST_TypeDef
  * @retval None
  */
void ll_ust_timer_pwm0_pol_enable(UST_TypeDef *p_ust);

/**
  * @brief  ust_timer_pwm0_pol_disable
  * @param  p_ust : pointer to the hardware UST_TypeDef
  * @retval None
  */
void ll_ust_timer_pwm0_pol_disable(UST_TypeDef *p_ust);

/**
  * @brief  Link layer UST TIMER PWM0 POL get
  * @param  p_uart: The structure pointer of the UST0 is selected
  * @retval result
  */
#define LL_UST_TIMER_PWM0_POL_GET(p_ust)                    ((p_ust)->UST_CON0 & LL_UST_CON0_TIMER_PWM0_POL)

/**
  * @brief  ust_timer_prd_buf_set
  * @param  p_ust : pointer to the hardware UST_TypeDef
  * @retval None
  */
void ll_ust_timer_prd_buf_set(UST_TypeDef *p_ust, u16 value);

/**
  * @brief  Link layer UST TIMER PRD BUF get
  * @param  p_uart: The structure pointer of the UST0 is selected
  * @retval result
  */
#define LL_UST_TIMER_PRD_BUF_GET(p_ust)                     (LL_UST_TIMER_PRD_BUF((p_ust)->UST_PRD_BUF))

/**
  * @brief  ust_pwm0_duty_buf_set
  * @param  p_ust : pointer to the hardware UST_TypeDef
  * @retval None
  */
void ll_ust_pwm0_duty_buf_set(UST_TypeDef *p_ust, u16 value);

/**
  * @brief  ust_pwm1_duty_buf_set
  * @param  p_ust : pointer to the hardware UST_TypeDef
  * @retval None
  */
void ll_ust_pwm1_duty_buf_set(UST_TypeDef *p_ust, u16 value);

/**
  * @brief  ust_pwm2_duty_buf_set
  * @param  p_ust : pointer to the hardware UST_TypeDef
  * @retval None
  */
void ll_ust_pwm2_duty_buf_set(UST_TypeDef *p_ust, u16 value);

/**
  * @brief  ust_pwm3_duty_buf_set
  * @param  p_ust : pointer to the hardware UST_TypeDef
  * @retval None
  */
void ll_ust_pwm3_duty_buf_set(UST_TypeDef *p_ust, u16 value);

/**
  * @brief  ust_timer_pwm_bit_stream_buf_write
  * @param  p_ust : pointer to the hardware UST_TypeDef
  * @retval None
  */
void ust_timer_pwm_bit_stream_buf_write(UST_TypeDef *p_ust, u32 value);

/**
  * @brief  Link layer UST TIMER PWM_LED_FRAME_CNT get
  * @param  p_uart: The structure pointer of the UST0 is selected
  * @retval result
  */
#define LL_UST_TIMER_PWM_LED_FRAME_CNT_GET(p_ust)           (((p_ust)->UST_CMP23_BUF>>24)&0x7)

/**
  * @brief  Link layer UST TIMER PWM_LED_BIT_CNT get
  * @param  p_uart: The structure pointer of the UST0 is selected
  * @retval result
  */
#define LL_UST_TIMER_PWM_LED_BIT_CNT_GET(p_ust)             (((p_ust)->UST_CMP23_BUF>>16)&0x1F)

/**
  * @brief  ust_timer_pwm_led_frame_set
  * @param  p_ust : pointer to the hardware UST_TypeDef
  * @retval None
  */
void ust_timer_pwm_led_frame_set(UST_TypeDef *p_ust, u8 value);

/**
  * @brief  Link layer UST TIMER PWM_LED_FRAME_SET get
  * @param  p_uart: The structure pointer of the UST0 is selected
  * @retval result
  */
#define LL_UST_TIMER_PWM_LED_FRAME_SET_GET(p_ust)           (((p_ust)->UST_CMP23_BUF>>8)&0x7)

/**
  * @brief  ust_timer_pwm_led_bit_set
  * @param  p_ust : pointer to the hardware UST_TypeDef
  * @retval None
  */
void ust_timer_pwm_led_bit_set(UST_TypeDef *p_ust, u8 value);

/**
  * @brief  ust_timer_pwm_bit_stream_set
  * @param  p_ust : pointer to the hardware UST_TypeDef
  * @retval None
  */
void ust_timer_pwm_led_bit_stream_set(UST_TypeDef *p_ust, u32 value);

/**
  * @brief  ust_timer_pwm_bit_stream_buf_set
  * @param  p_ust : pointer to the hardware UST_TypeDef
  * @retval None
  */
void ust_timer_pwm_led_bit_stream_buf_set(UST_TypeDef *p_ust, u32 value);

/**
  * @brief  Link layer UST TIMER PWM_LED_BIT_SET get
  * @param  p_uart: The structure pointer of the UST0 is selected
  * @retval result
  */
#define LL_UST_TIMER_PWM_LED_BIT_SET_GET(p_ust)             (((p_ust)->UST_CMP23_BUF>>0)&0x1F)


/**
  * @brief  TIMER counting cycle control
  * @param  p_ust : pointer to the hardware UST_TypeDef
  * @param  data : overloaded data
  * @retval None
  */
void ll_ust_timer_prd_set(UST_TypeDef *p_ust, u16 data);

/**
  * @brief  ust timer prd get
  * @param  p_uart: The structure pointer of the UST0 is selected
  * @retval result
  */
#define LL_UST_STA_TIMER_PRD_GET(p_ust)                     (LL_UST_BAUD_TIMER_PRD((p_ust)->UST_BAUD))

/**
  * @brief  Write begins when idle.
  * @param  p_ust : pointer to the hardware UST_TypeDef
  * @retval None
  */
void ll_ust_timer_start(UST_TypeDef *p_ust);

/**
  * @brief  Writing stopped while working.
  * @param  p_ust : pointer to the hardware UST_TypeDef
  * @retval None
  */
void ll_ust_timer_stop(UST_TypeDef *p_ust);


/**
  * @brief  ust uart mode config.
  * @param  p_ust : pointer to the hardware UST_TypeDef
  * @param  baudrate : uart baud rate
  * @retval None
  */
void ll_ust_uart_config(UST_TypeDef *p_ust, u32 baudrate);


/**
  * @brief  ust done pending get
  * @param  p_uart: The structure pointer of the UST0 is selected
  * @retval result
  */
#define LL_UST_STA_DONE_PENDING_GET(p_ust)                  ((p_ust)->UST_STA & LL_UST_STA_DONE_PENDING)

/**
  * @brief  ust done pending clear
  * @param  p_uart: The structure pointer of the UST0 is selected
  * @retval result
  */
#define LL_UST_STA_DONE_PENDING_CLR(p_ust)                  ((p_ust)->UST_STA = LL_UST_STA_DONE_PENDING)

/**
  * @brief  ust uart buffer overflow pending get
  * @param  p_uart: The structure pointer of the UST0 is selected
  * @retval result
  */
#define LL_UST_STA_UART_BUFF_OVF_PENDING_GET(p_ust)         ((p_ust)->UST_STA & LL_UST_STA_UART_BUFF_OVF_PENDING)

/**
  * @brief  ust uart buffer overflow pending clear
  * @param  p_uart: The structure pointer of the UST0 is selected
  * @retval result
  */
#define LL_UST_STA_UART_BUFF_OVF_PENDING_CLR(p_ust)         ((p_ust)->UST_STA = LL_UST_STA_UART_BUFF_OVF_PENDING)

/**
  * @brief  ust uart frame error pendig get
  * @param  p_uart: The structure pointer of the UST0 is selected
  * @retval result
  */
#define LL_UST_STA_UART_FERR_PENDING_GET(p_ust)             ((p_ust)->UST_STA & LL_UST_STA_UART_FERR_PENDING)

/**
  * @brief  ust uart frame error pendig clear
  * @param  p_uart: The structure pointer of the UST0 is selected
  * @retval result
  */
#define LL_UST_STA_UART_FERR_PENDING_CLR(p_ust)             ((p_ust)->UST_STA = LL_UST_STA_UART_FERR_PENDING)

/**
  * @brief  ust buffer pending get
  * @param  p_uart: The structure pointer of the UST0 is selected
  * @retval result
  */
#define LL_UST_STA_BUFFER_PENDING_GET(p_ust)                ((p_ust)->UST_STA & LL_UST_STA_BUFFER_PENDING)

/**
  * @brief  ust timer start pending get
  * @param  p_uart: The structure pointer of the UST0 is selected
  * @retval result
  */
#define LL_UST_STA_START_PENDING_GET(p_ust)                 ((p_ust)->UST_STA & LL_UST_STA_START_PENDING)




/**
  * @}
  */
  
/** @defgroup UST_LL_Data_Transfers UST LL Data transfers functions
  * @brief    UST LL Data transfers functions 
  *
@verbatim   
  ===============================================================================
                            Data transfers functions
  ===============================================================================  

    This subsection provides a set of functions allowing to manage the UST data 
    transfers and receive.
  
@endverbatim
  *
  * @{
  */

/**
  * @}
  */

/**
  * @}
  */

#ifdef __cplusplus
}
#endif

/**
  * @}
  */

/**
  * @}
  */

#endif //__JS32T031_LL_UST_H

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